A so-called cross-point memory cell unit constituted of a plurality of nonvolatile memory cells is well-known. The cross-point memory cell unit is constituted of
a plurality of first wires (bit lines) extending in a first direction,
a plurality of second wires (word line) that are disposed separately from the first wires in upper and lower directions and extend in a second direction unlike the first wires, and
a nonvolatile memory cell that is disposed in a region in which the first wires and the second wires overlap one another and connected to the first wires and the second wires. Information is written in and erased from the nonvolatile memory cell on the basis of a direction of voltage applied between the first wires and the second wires or a direction of current flowing between the first wires and the second wires.
In order to reduce a chip area in such a cross-point memory cell unit, a memory cell unit as disclosed in Japanese Patent Application Laid-open No. 2009-223971 includes two column-related control circuits and two row-related control circuits directly below a plurality of nonvolatile memory cells that constitutes it. The two column-related control circuits and the two row-related control circuits are arranged in a checker board form.
By the way, an indication generally used for expressing integration of semiconductor apparatuses is a minimum feature size “F”. A configuration that can provide highest-density memory cells in the cross-point memory cell unit is a configuration in which the pitch of the bit line is 2F, the pitch of the word line is 2F, and an occupation area of a single memory cell is 4F2. It is necessary to form contact holes for connect the control circuits to the bit and word lines. It is often necessary to set a width between the wires to be larger than the minimum feature size “F” around the contact holes due to constraints (design rules) for enhancing manufacturing yield in manufacturing processes for semiconductor apparatuses. When a contact hole is formed at an end portion of a certain bit line, another contact hole cannot be formed at an end portion of a bit line adjacent to this bit line on the same side. It is because a distance between the bit line, which is widened for forming the contact hole therein, and the adjacent bit line would be smaller than the minimum feature size “F”. Thus, in order to connect all the bit lines to the control circuits, an arrangement as schematically shown in FIG. 49 is employed, for example. In this arrangement, contact holes of odd-numbered bit lines as viewed in a plane are provided at end portions thereof on an upper side of FIG. 49. On the other hand, contact holes of even-numbered bit lines as viewed in the plane are provided at end portions thereof on a lower side of FIG. 49. The same applies to the word lines. Specifically, contact holes of odd-numbered word lines are provided at end portions thereof on a left side of FIG. 49 and contact holes of even-numbered word lines are provided at end portions thereof on a right side of FIG. 49.